module mux4to1(sel, d, q);

input[1:0] sel;
input[3:0] d;
output q;

reg q;
wire[1:0] sel;
wire[3:0] d;

always @(sel or d)
begin
	case(sel)
	1: q = d[0];
	2: q = d[1];
	3: q = d[2];
	4: q = d[3];
	default: q = 0;
	endcase

end

endmodule