module assn2FSM(clk, rst, Y, X, Z);
	input clk;
	input rst;
	input y;
	input x;
	

	// states value
	parameter s1 = 4'b0001;
	parameter s3 = 4'b0011;
	parameter s5 = 4'b0101;
	parameter s6 = 4'b0110;
	parameter s8 = 4'b1000;
	parameter s10 = 4'b1010;

	reg [3:0] Z;
	reg [1:0] state;
	reg [1:0] next_state;


	// current state logic
	always @(posedge clk or posedge rst)
	begin
		if (rst) state <= s3;
		else state <= next_state;
	end


	
	// next state logic
	always @(state or Y or X)
	begin
		casex(state)
		s1: if ((Y==x)&(X0=x))
			next_state = s8;

		s3: if ((Y==1)&(X==1))
			next_state = s5;
		    else ((Y==1)&(X==0))
			next_state = s1;

		s5: if ((Y==x)&(X==x))
			next_state = s5;

		s6: if ((Y==x)&(X==x))
			next_state = s10;

		s8: if ((Y==0)&(X==1))
			next_state = s5;
		    else if ((Y=0)&(X=0))
			next_state = s6;
		    else ((Y==1)&(X==x))

			next_state = s10;
		s10: if ((Y==x)&(X==x))
			next_state = s10;

		endcase
	end



	// output logic
	always @(state)
	begin
		case(state)
		s1: Z = 4'b0001;
		s3: Z = 4'b0000;
		s5: Z = 4'b0001;
		s6: Z = 4'b0010;
		s8: Z = 4'b0001;
		s10: Z = 4'b0101;
		endcase
	end



endmodule